To reduce cost, improve speeds, and/or conserve power, manufacturers shrink the size or geometries of negative AND (NAND) flash storage up to 15 nm (after 15 nm, NAND goes to 3D stackable for density improvements, the feature size itself does not shrink). As NAND flash storage geometries get smaller, some adverse effects become more noticeable, such as the unintentional addition of charge (more generally, the introduction of noise) to cells, crosstalk or cell-to-cell interference, etc. Thus, smaller-featured devices can have higher error rates and poor data retention. Techniques to overcome such adverse effects would be desirable.